#include <targets/lpc21xx.h>
#include "enc28j60.h"
#include "spi.h"
Go to the source code of this file.
Defines | |
| #define | SEL_MAC(x) (x==TRUE) ? (IO0CLR=CS_ENC28J60) : (IO0SET =CS_ENC28J60) |
| #define | ERRATAFIX SetBitField(ECON1, ECON1_TXRST);ClrBitField(ECON1, ECON1_TXRST);ClrBitField(EIR, EIR_TXERIF | EIR_TXIF) |
Functions | |
| static u08 | ReadETHReg (u08 bytAddress) |
| ReadETHReg. | |
| static u08 | ReadMacReg (u08 bytAddress) |
| ReadMacReg. | |
| static u16 | ReadPhyReg (u08 address) |
| Read from PHY reg. | |
| static u16 | ReadMacBuffer (u08 *bytBuffer, u08 byt_length) |
| Read bytes from MAC data buffer. | |
| static u08 | WriteCtrReg (u08 bytAddress, u08 bytData) |
| Write to a control reg . | |
| static u08 | WritePhyReg (u08 address, u16 data) |
| Write to phy Reg. | |
| static u16 | WriteMacBuffer (u08 *bytBuffer, u16 ui_len) |
| Write bytes to MAC data buffer.[UNTESTED]. | |
| static void | ResetMac (void) |
| ResetMac. | |
| static u08 | SetBitField (u08 bytAddress, u08 bytData) |
| Set bit field. | |
| static u08 | ClrBitField (u08 bytAddress, u08 bytData) |
| Clear bit field on ctr registers. | |
| static void | BankSel (u08 bank) |
| Bank Select. | |
| void | initMAC (void) |
| Initialise the MAC. | |
| u16 | MACWrite (u08 *ptrBuffer, u16 ui_Len) |
| Writes a packet to the ENC28J60. | |
| u08 | MACRead (u08 *ptrBuffer) |
| Tries to read a packet from the ENC28J60. | |
Variables | |
| const u08 | bytMacAddress [6] = {0x01,0x01,0x01,0x01,0x01,0x01} |
| TXSTATUS | TxStatus |
Definition in file enc28j60.c.
| #define ERRATAFIX SetBitField(ECON1, ECON1_TXRST);ClrBitField(ECON1, ECON1_TXRST);ClrBitField(EIR, EIR_TXERIF | EIR_TXIF) |
| #define SEL_MAC | ( | x | ) | (x==TRUE) ? (IO0CLR=CS_ENC28J60) : (IO0SET =CS_ENC28J60) |
MACRO for selecting or deselecting chip select for the ENC28J60. Some HW dependancy.
Definition at line 41 of file enc28j60.c.
Referenced by ClrBitField(), ReadETHReg(), ReadMacBuffer(), ReadMacReg(), ResetMac(), SetBitField(), WriteCtrReg(), and WriteMacBuffer().
| static void BankSel | ( | u08 | bank | ) | [static] |
Bank Select.
Description: Select the required bank within the ENC28J60
| bank | Value between 0 and 3. |
Definition at line 517 of file enc28j60.c.
References ReadETHReg(), and WriteCtrReg().
Referenced by initMAC(), MACRead(), MACWrite(), ReadPhyReg(), and WritePhyReg().
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| static u08 ClrBitField | ( | u08 | bytAddress, | |
| u08 | bytData | |||
| ) | [static] |
Clear bit field on ctr registers.
Description: Sets the bit/s at the address register. Assumes correct bank has been selected.
| bytAddress | Address of registed where bit is to be set | |
| bytData | Sets all the bits high. |
Definition at line 490 of file enc28j60.c.
References SEL_MAC, and SPIWrite().
Referenced by MACWrite(), and ReadPhyReg().
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| void initMAC | ( | void | ) |
Initialise the MAC.
Description:
a) Setup SPI device. Assume Reb B5 for sub 8MHz operation
b) Setup buffer ptrs to devide memory in In and Out mem
c) Setup receive filters (accept only unicast).
d) Setup MACON registers (MAC control registers)
e) Setup MAC address f) Setup Phy registers
Definition at line 59 of file enc28j60.c.
References BankSel(), bytMacAddress, initSPI(), ResetMac(), SetBitField(), WriteCtrReg(), and WritePhyReg().
Referenced by init2106().
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| u08 MACRead | ( | u08 * | ptrBuffer | ) |
Tries to read a packet from the ENC28J60.
Description: If a valid packet is available in the ENC28J60 this function reads the packet into a buffer. The memory within the ENC28J60 will then be released. This version of the driver does not use interrupts so this function needs to be polled.
1) Read packet count register. If >0 then continue else return.
2) Read the current ERXRDPTR value.
3) Write this value into ERDPT.
4) First two bytes contain the ptr to the start of next packet. Read this value in.
5) Calculate length of packet.
6) Read in status byte into private variable.
7) Read in packet and place into buffer.
8) Free up memory in the ENC.
| ptrBuffer | ptr to buffer of bytes where the packet should be read into. |
Definition at line 216 of file enc28j60.c.
References BankSel(), RXSTATUS::bits, RXSTATUS::ByteCount, RXSTATUS::NextPacket, ReadETHReg(), ReadMacBuffer(), SetBitField(), RXSTATUS::v, and WriteCtrReg().
Referenced by main().
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| u16 MACWrite | ( | u08 * | ptrBuffer, | |
| u16 | ui_Len | |||
| ) |
Writes a packet to the ENC28J60.
Description: Writes ui_len bytes of data from ptrBufffer into ENC28J60. puts the necessary padding around the packet to make it a legit MAC packet.
1) Program ETXST.
2) Write per packet control byte.
3) Program ETXND.
4) Set ECON1.TXRTS.
5) Check ESTAT.TXABRT.
| ptrBuffer | ptr to byte buffer. | |
| ui_Len | Number of bytes to write from buffer. |
Definition at line 131 of file enc28j60.c.
References BankSel(), TXSTATUS::bits, ClrBitField(), ERRATAFIX, TXSTATUS::LateCollision, ReadETHReg(), ReadMacBuffer(), SetBitField(), TxStatus, TXSTATUS::v, WriteCtrReg(), and WriteMacBuffer().
Referenced by main().
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| static u08 ReadETHReg | ( | u08 | bytAddress | ) | [static] |
ReadETHReg.
Description: Reads contents of the addressed ETH reg over SPI bus. Assumes correct bank selected.
| bytAddress | Address of register to be read |
Definition at line 265 of file enc28j60.c.
References SEL_MAC, SPIRead(), and SPIWrite().
Referenced by BankSel(), MACRead(), and MACWrite().
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| static u16 ReadMacBuffer | ( | u08 * | bytBuffer, | |
| u08 | byt_length | |||
| ) | [static] |
Read bytes from MAC data buffer.
Description: Reads a number of bytes from the ENC28J60 internal memory. Assumes auto increment is on.
| bytBuffer | Buffer to place data in. | |
| byt_length | Number of bytes to read. |
Definition at line 411 of file enc28j60.c.
References SEL_MAC, SPIRead(), and SPIWrite().
Referenced by MACRead(), and MACWrite().
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| static u08 ReadMacReg | ( | u08 | bytAddress | ) | [static] |
ReadMacReg.
Description: Read contents of addressed MAC register over SPI bus. Assumes correct bank selected.
| bytAddress | Address of register to read. |
Definition at line 291 of file enc28j60.c.
References SEL_MAC, SPIRead(), and SPIWrite().
Referenced by ReadPhyReg().
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| static u16 ReadPhyReg | ( | u08 | address | ) | [static] |
Read from PHY reg.
Description: No direct access allowed to phy registers so the folling process must take place.
1) Write address of phy reg to read from into MIREGADR.
2) Set MICMD.MIIRD bit and wait 10.4uS.
3) Clear MICMD.MIIRD bit.
4) Read data from MIRDL and MIRDH reg.
| address |
Definition at line 351 of file enc28j60.c.
References BankSel(), ClrBitField(), ReadMacReg(), SetBitField(), and WriteCtrReg().
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| static void ResetMac | ( | void | ) | [static] |
ResetMac.
Description: Sends command to reset the MAC.
Definition at line 537 of file enc28j60.c.
References SEL_MAC, and SPIWrite().
Referenced by initMAC().
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| static u08 SetBitField | ( | u08 | bytAddress, | |
| u08 | bytData | |||
| ) | [static] |
Set bit field.
Description: Sets the bit/s at the address register. Assumes correct bank has been selected.
| bytAddress | Address of registed where bit is to be set | |
| bytData | Sets all the bits high. |
Definition at line 463 of file enc28j60.c.
References SEL_MAC, and SPIWrite().
Referenced by initMAC(), MACRead(), MACWrite(), and ReadPhyReg().
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| static u08 WriteCtrReg | ( | u08 | bytAddress, | |
| u08 | bytData | |||
| ) | [static] |
Write to a control reg .
Description: Writes a byte to the address register. Assumes that correct bank has all ready been selected
| bytAddress | Address of register to be written to. | |
| bytData | Data to be written. |
Definition at line 383 of file enc28j60.c.
References SEL_MAC, and SPIWrite().
Referenced by BankSel(), initMAC(), MACRead(), MACWrite(), ReadPhyReg(), and WritePhyReg().
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| static u16 WriteMacBuffer | ( | u08 * | bytBuffer, | |
| u16 | ui_len | |||
| ) | [static] |
Write bytes to MAC data buffer.[UNTESTED].
Description: Reads a number of bytes from the ENC28J60 internal memory. Assumes auto increment is on.
| bytBuffer | ||
| ui_len |
Definition at line 437 of file enc28j60.c.
References SEL_MAC, and SPIWrite().
Referenced by MACWrite().
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| static u08 WritePhyReg | ( | u08 | address, | |
| u16 | data | |||
| ) | [static] |
Write to phy Reg.
Description: Writing to PHY registers is different to writing the other regeisters in that the registers can not be accessed directly. This function wraps up the requirements for writing to the PHY reg.
1) Write address of phy reg to MIREGADR.
2) Write lower 8 bits of data to MIWRL.
3) Write upper 8 bits of data to MIWRL.
| address | ||
| data |
Definition at line 325 of file enc28j60.c.
References BankSel(), and WriteCtrReg().
Referenced by initMAC().
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| const u08 bytMacAddress[6] = {0x01,0x01,0x01,0x01,0x01,0x01} |
MAC address. Will move this some where else
Definition at line 20 of file enc28j60.c.
Referenced by initMAC().
1.5.2